An Introduction to Using Logic Gates in LTspice

SPICE simulators are intended primarily for analog circuitry. Despite that, there are many situations—designing a mixed-signal circuit, for example—where digital components can enhance a SPICE simulation. For that reason, the LTspice component library has a directory called Digital. As shown in Figure 1, it contains several digital components.

 

Figure 1. The LTspice digital component directory.

 

When you start using these components, however, you may discover they’re less user-friendly than they seem. Drawing on the relevant LTspice documentation, this article will explore some of the less-than-obvious aspects of incorporating digital components into LTspice schematics. More specifically, we’ll focus on how to connect these components so that they behave properly during your simulations.

 

A Five-Input AND Gate?

In addition to inverting gates and buffers, LTspice's basic logic functions include the following multiple-input gates:

• AND
• OR
• XOR

Figure 2 shows the AND, OR, and XOR components arranged from left to right.

 

Figure 2. From left to right: LTspice’s AND, OR, and XOR gates.

 

All three gates in Figure 2 have eight terminals: five inputs, two outputs, and one attached without a label to the bottom of the symbol. The eighth, unlabeled terminal serves as the device’s common terminal. A five-input, two-output gate definitely isn’t what comes to my mind when I think of a standard logic device, but the intention here is that each component be adaptable to a multitude of circuit applications.

For example, the LTspice documentation states that the AND device “acts as 12 different types of AND gates.” What it means is that the LTspice AND component can function as a two-input, three-input, four-input, or five-input AND gate. Each of these four input configurations can then be combined with one of three output configurations:

1. A non-inverted output signal.
2. An inverted output signal.
3. Complementary output signals.

This gives us a total of 12 input/output configurations.

To function normally within the analog environment of SPICE, these digital components need to allow some sort of coherent path for current. For that reason, the documentation specifies that current is sourced or sunk from the outputs and returned through the common terminal. No positive supply connection is needed, hence the conspicuous absence of a positive power supply pin anywhere in Figure 2.

 

How to Handle Unused Inputs

Few simulations actually need a five-input logic gate, so you can expect to have one or more unused inputs. When that’s the case, the proper procedure is to connect any unused inputs to the device’s common terminal. Doing so tells LTspice to eliminate those inputs from the simulation.

Consider the OR gate in Figure 3. Its common terminal is connected to ground and its three unused inputs are connected to the common terminal.

 

Figure 3. A two-input OR gate. Its three unused inputs are properly connected to the common terminal.

 

As far as simulation computations are concerned, this device is truly a two-input OR gate. Because they’re connected to the common terminal, the unused inputs will affect neither the circuit’s electrical behavior or the simulation speed.

By contrast, the diagram in Figure 4 shows a non-optimal way of handling unused inputs. The unused inputs are connected to a 0 V logic-low voltage instead of to the OR gate’s common terminal.

 

Figure 4. OR gate with unused inputs connected to 0 V rather than to the common terminal.

 

Because the three unused inputs are logic-low, they won’t affect the OR gate’s electrical behavior. They will contribute to simulation complexity, however.

Finally, Figure 5 is both functionally problematic and non-optimal in terms of simulation efficiency. The three unused inputs are once again connected to a 0 V node rather than to the grounded common terminal. This time, though, we’re looking at an AND gate rather than an OR gate.

 

Figure 5. AND gate with unused inputs connected to a 0 V node instead of the gate’s common terminal.

 

Because this is an AND gate, tying the unused inputs to a 0 V supply or signal will interfere with the device’s operation. The AND gate’s output will never be logic-high, no matter the state of the two active inputs—the other three inputs are always logic-low, and LTspice won’t exclude them from the simulation unless they’re connected to the common terminal.

The flip side is that connecting an input to the common terminal always removes it from the simulation. If the gate’s common terminal is connected to ground, and you connect one of the two active inputs to ground in an attempt to make it logic-low, you will not make this input pin logic-low. Instead, you’ll eliminate it. The device will then behave like a buffer (V_OUT = V_IN).

If you really need to optimize simulation performance, you can also eliminate unused outputs from the simulation by connecting them directly to the gate’s common terminal.

 

Wrapping Up

I hope that this article helps you to avoid confusing failures or unexpected behavior when incorporating logic gates into your LTspice circuits. In the next article of this series, we’ll discuss how to customize these components’ electrical behavior.

 

Background of featured image used courtesy of Adobe Stock; all other images used courtesy of Robert Keim