Three Companies Collab on Near-Zero-Degree Cryogenic CMOS Circuits
In order to tackle quantum problems, Siemens, SemiWise, and SureCore are making CMOS circuits much cooler.
Three companies—Siemens, SemiWise, and SureCore—have united to create cryogenic CMOS circuits that interface directly with quantum computing qubits.
Scaled-up quantum computers require densely integrated CMOS circuits that can operate at cryogenic temperatures. Image (modified) used courtesy of Siemens
This article discusses how each of these companies lent their unique expertise to develop cryogenic CMOS IP for quantum computing. We'll also address the current limitations of cryogenic CMOS and how the advent of cryoCMOS could give quantum computing the boost it needs to scale upward.
Quantum Computing, CMOS, and the Challenge of Heat
Quantum computing leverages small-particle mechanics to accomplish complex calculations. As a result, quantum systems are susceptible to outside forces, requiring extremely low temperatures on the order of single-digit Kelvin to maintain quantum information.
Typically, CMOS circuits and quantum computers are isolated from each other and are connected via long coaxial cables. While this works on a small scale, this technique is difficult to integrate densely, making larger quantum deployments impractical without dedicated CMOS chips.
At cryogenic temperatures, transistors exhibit different operating characteristics that can render a room-temperature design useless at low temperatures. Image used courtesy of IEEE Transactions on Electron Devices
This isolation between CMOS circuits and quantum computers also creates many challenges on the system level. On one hand, the cryogenic temperatures are well outside the normal CMOS operation range, requiring advanced SPICE models to perform CMOS simulations. On the other hand, any power dissipated in the CMOS circuit can create heat and noise, potentially impacting the quantum information stored in qubits.
As a result, compatible CMOS circuits must simultaneously withstand low temperatures and produce as little heat as possible to prevent overloading the cryogenic chambers.
Multi-Pronged IP Development
In order to tackle the cryoCMOS problem, Siemens, SemiWise, and SureCore have partnered to develop cryoCMOS IP for quantum designers to leverage in next-generation systems. Using SemiWise’s transistor modeling IP (likely including flat-field and channel-last transistor technology), SureCore will develop its CryoIP product line. This resulting product line should ultimately aid designers in developing quantum-compatible CMOS circuits.
SemiWise’s flat-field transistors offer advantages over traditional FETs that could be beneficial at cryogenic temperatures. Image used courtesy of SemiWise
Both organizations will use Siemens’ IC design software to provide advanced capabilities when operating near absolute zero. Siemens' Analog FastSPICE platform verifies the cryogenic CMOS circuits, while the Solido Design Environment can accomplish the custom cell design. SureCore is currently working toward a CryoIP tapeout and is expected to leverage the GlobalFoundries’ 22FDX PDK.
An Experiment in Scalability
Regardless of whether or not the CryoIP line works after the first tapeout, the results of the tapeout could be instrumental in unifying custom silicon with quantum computing. If a robust line of IP is available, quantum computer designers may have a new method of controlling quantum systems that allows for unprecedented scalability in next-generation quantum computers.
