Synopsys Claims Industry’s First PCI Express 7.0 IP Set

With the goal of supporting the AI and data booms, Synopsys has unveiled its new PCI Express (PCIe) 7.0 IP offerings. These new IP blocks, ranging from the PCIe Gen 7 PHY to integrated security and encryption, offer designers cookie-cutter solutions to continue advancing data-handling capabilities in cutting-edge environments such as data centers.

A crucial technology for the computing industry, PCI Express reached its 20th anniversary last year.
 

As model complexity and data needs continue to grow, the improved latency and throughput of PCIe Gen 7 is critical to support continued development and could be enabled by Synopsys’s newest IP offerings.

 

While some designers consider data to be as valuable as gold, others feel that data is the new garbage, since it can be found in excess and requires careful examination to determine if it is valuable. As a result, to separate the data wheat from the chaff, data centers and high-performance computers must be capable of withstanding unprecedented data loads, something that could be much easier thanks to the PCIe 7.0 standard and the new Synopsys IP.

To learn more about Synopsys’s new offerings, we sat down with Priyank Shukla, principal product manager, and Manmeet Walia, executive director at Synopsys. We will share some of what we learned here, as well as highlight key points to give readers a sense of how the IP can be used to support continued developments in the computing sector.

 

Supporting Data-Heavy Software

The PCIe standard has seen a considerable amount of usage thanks to the ability to generalize devices and allow inter-processor communication. Instead of needing to define a manufacturer-specific communication protocol, developers can make use of the standard to ensure their devices work well with many others.

When discussing the benefits and need for PCIe in modern computers, Shukla said, “The underlying technology for all of these is PCIe, which is moving from Gen 6 to Gen 7. And Synopsys is making this technology, PCIe Gen 7, available to the whole ecosystem.”

 

In HPC or data-center configurations, PCIe plays a critical role in moving data where necessary. As a result, advancements in PCIe interconnects can translate to improved overall performance.

 

Like many cases where needs evolve over time, the PCIe standard has seen considerable evolution over the years. And, with the upcoming PCIe 7.0 standard, the protocol can be used to transfer more data more robustly. As a result, Synopsys’s newest IP release offers designers with a bevy of performance boosts to meet the standard.

 

Balancing Speed and Efficiency

The new Synopsys PCIe IP includes several new devices for designers to use. Namely, the PCIe 7.0 controller and PHY allow for low latency and improved efficiency, while the Integrated Data Encryption (IDE) and Verification blocks allow designers to ensure that their devices perform as expected.

In terms of speed, the Synopsys PCIe Gen 7 IP supports up to 512 GB/s data speeds, leveraging PAM-4 signaling and up to x16 lane configurations. This is demonstrated in a Synopsys PCIe YouTube video from DesignCon 2024. In addition, the IP improves efficiency, with a reported 50% improved power efficiency compared to previous generations.

 

The Synopsys PCIe Gen 7 eye diagram shows operation at 128 GT/s, highlighting the potential for the technology to be used to support data-heavy computing needs.

 

This tradeoff is a key metric that Synopsys hoped to balance. “This whole thing is getting more complex,” said Walia.

 

“There’s so much pressure on the four key technical metrics that we talked about, the power, the latency, the performance, and the area. And depending on what the application is, these four metrics can go in some order. But typically, latency and power stay on the top.”

 

The Synopsys release further includes security IP, including the IDE and Verification blocks. The PCIe 7.0 IP is also available with support for the Arm Confidential Compute architecture, allowing for more usage. The Synopsys PCIe Gen 7 solutions will be demonstrated at the PCI-SIG Developers Conference, running this week, June 12-13, in Santa Clara, CA.

 

Expanding the Utility of PCIe

While no one could say that PCIe has not shown its uses for many years, designers are still finding new ways to add the standard to more applications. Particularly, as computing becomes more and more distributed, PCIe buses may now need to extend beyond a rack PCB and move to another (or many other) racks using optical links. 

And, while this may not have been practical in previous years, the advancements from Synopsys could allow PCIe 7.0 to be used in more use cases, shown by Shukla who said, “What we are seeing now is for Scale Up Network, there are requests that they want PCIe to go from one rack to another. And that can be more efficiently done if PCIe runs over optics.”

 

“That’s the message we are providing today is we have demonstrated this PCIe with fiber optics with PCIe Gen 7. So, if your deployment needs PCIe fiber optics, Synopsys’s solution provides a way forward.”

 

All images used courtesy of Synopsys