Synaptics Launches ‘New Class of MCUs’ That Run Multimodal Edge AI

Synaptics has introduced the Astra SR200 Series, a family of edge AI processors that the company describes as a new device class: the xMCU. The series targets AI wearables, battery-powered sensors, connected cameras, streamers, and industrial vision and voice systems.

The new series includes the Astra SR210, SR230, and SR250. 

Synaptics says the SR200 runs multimodal AI that normally needs a Linux-based applications processor and discrete DRAM.

Three Tiers, One Footprint

The series comprises three pin-compatible lines that share a single SDK. The SR210 delivers 200 GOPS and targets power-optimized, always-on voice and sensing. The SR230 raises AI throughput to 300 GOPS and adds vision, display, and optional audio for mainstream multimodal devices. At the top, the SR250 reaches 400 GOPS and adds dual vision and display paths.

According to the product brief, the CPU complex combines an Arm Cortex-M85 at 800 MHz with a Cortex-M52 at 200 MHz. An optional Cadence Tensilica HiFi 5 DSP running at 400 MHz handles audio and acoustic ML. AI inference runs on Synaptics' Torq AI engine, which integrates Google Research's Coral NPU instead of an Arm Ethos core. It supports INT8, INT16, and BFLOAT16 data types, as well as CNN and transformer networks, programmed through an open-source MLIR/IREE-based compiler.

Block diagram of the new Astra SR200 Series. 

Vision comes through two 2-lane MIPI CSI-2 interfaces at up to 2.5 Gbps per lane, feeding dual ISPs (one for AI vision, one for human viewing) and H.264/JPEG codecs. A 2.5D GPU drives two 2-lane MIPI DSI outputs, supporting one 1920 x 1080 display at 60 Hz or two at 30 Hz. Audio support includes two I2S/TDM ports and three PDM interfaces for up to six digital microphones, along with hardware voice activity detection and a dedicated mute pin.

Other I/O includes USB 2.0, eMMC 5.1, octal SPI, I3C, more than 140 GPIOs, and a RISC-V I/O engine for custom peripherals. Industrial variants add gigabit Ethernet with TSN and two CAN-FD controllers, while security includes anti-tamper detection and secure boot, with PSA Level 3 and Common Criteria EAL4+ certification listed as targets.

Why Custom DRAM?

On-chip SRAM is fast but costly in die area, so most AI-capable MCUs top out at a few megabytes. Larger vision models, transformers, and frame buffers quickly outgrow that, pushing designers to external PSRAM or flash over octal SPI. Those links deliver at most hundreds of megabytes per second (Renesas, for example, quotes up to 333 MB/s for the xSPI ports on its RA8P1), limiting how fast an NPU can be fed weights and activations.

The SR200 pairs up to 8 MB of shared SRAM with more than 700 KB of local memory across the processors and DSP, plus what Synaptics calls "extensible, high-bandwidth, high-capacity custom DRAM that scales to hundreds of megabytes." The device is built as a multi-die system-in-package that combines compute, power management, and memory, so the DRAM sits in the same package as the MCU.

Synaptics says the DRAM can run workloads at a third of the power of typical system DRAM, but it hasn't yet published a bandwidth figure, a process node, or exact DRAM capacities per SKU, so the bandwidth advantage over external memory cannot yet be quantified.

The First Cortex-M85 and Cortex-M52 Pairing

Synaptics says the SR200 is the industry's first device to pair the Arm Cortex-M85 and Cortex-M52. The M85, Arm's highest-performance Cortex-M core, handles control, multimedia, and burst compute. The M52, announced in November 2023, is its compact Helium-enabled core. Arm claims up to 5.6 x higher ML performance and up to 2.7 x higher DSP performance for it, and it's fully software-compatible with the M55 and M85.

Because both cores implement Helium, the M-Profile Vector Extension in Armv8.1-M, vector DSP, and ML code can run on either core. In the SR200, the M52 serves as the efficiency core for always-on sensor fusion, connectivity, and low-power inference, while a separate always-on domain handles voice activity detection, timekeeping, and wake-up. An integrated PMIC with DVFS manages four independent power domains. 

The SR200 steps well beyond the SR100 Series that Synaptics launched in March 2025. Those parts used a 400-MHz Cortex-M55, an Arm Ethos-U55 NPU in some variants, and up to 4 MB of system memory. Other high-end Cortex-M85 MCUs include Renesas' RA8P1, which runs at 1 GHz and pairs a 256 GOPS Ethos-U55 with 2 MB of SRAM. Alif's Ensemble E4, E6, and E8 parts use Cortex-M55 cores with the Ethos-U85 NPU.

All images used courtesy of Synaptics.