SureCore Balances Power and Cooling Costs With Cryogenic Memory
SureCore has announced a low-power, cryogenic SRAM to reduce the energy demands of AI workloads on data centers.
SureCore has announced a cryogenic ultra-low-power memory technology that drastically reduces power consumption and decreases the need for cooling infrastructure in data centers. SureCore ported and tuned the new embedded Static Random Access Memory (SRAM) using Semiwise's cryogenic transistor SPICE models. According to SureCore, the new memory can accommodate quantum computers, operating from 77K (-196°C) down to near absolute zero temperatures.
SureCore releases this new memory solution as SRAM becomes a popular memory technology for AI-focused data center processors. SRAM enables chips to access and manipulate information quickly, making it useful for tasks such as real-time data analysis and decision-making common in AI workloads.
SureCore partnered with Semiwise to test its new low-power SRAM through Semiwise's cryogenic transistor SPICE models.
One of the key challenges for data centers, however, is reducing the exorbitant costs to power these AI workloads. While developers are attempting to address this issue by cooling down data center processors, over half the cost benefits are lost at the expense of such extreme cooling. SureCore claims its low-power cryogenic memory technology can save up to 50% of the memory power in data centers, subsequently slashing thermal dissipation and cooling power costs.
SureCore’s Adds to Its CryoMem IP
The newly announced cryogenic SRAM is specifically designed for operation from 77K (about -196°C) down to 4K (about -269°C). Quantum computers must often operate at extremely low temperatures to eliminate thermal noise and vibrations. In its new product, SureCore re-characterized standard cell and IO cell libraries for operation at cryogenic temperatures, facilitating the adoption of an industry-standard RTL to GDSII physical design flow.
With this new memory solution, customers benefit from the SRAM's reduced power demands in standard and IO cells that can operate at very cold temperatures. SureCore aims to make its memory technology available as an IP via SureCore's CryoMem IP range.
The architecture of one of SureCore's other low-power SRAM IPs, PowerMiser.
The IP, part of an Innovate UK project led by SureCore, is set to undergo evaluation at cryogenic temperatures through upcoming test chips. By co-locating CryoCMOS control chips with qubits in the cryostat, SureCore reduces the need for extensive and performance-limiting cabling, addressing a significant barrier to scaling quantum computing systems.
SureCore's Unique Approach to SRAM
Designers can reduce SRAM supply voltage and power consumption in circuitry using a method known as dynamic voltage and frequency scaling (DVFS). This approach involves shutting down non-essential circuitry when a device is in a standby state, for instance.
For memory, DVFS doesn’t work as well because memory must retain data and reliably read and write from it at all times. Once the supply voltage is reduced below a certain threshold, memory is not guaranteed to operate correctly. Furthermore, manufacturing variation due to factors such as line edge roughness, random dopant fluctuation, and metal gate granularity means that each bit cell will have a slightly different behavior than even its adjacent neighbor.
Designers often use Monte Carlo simulations to model this variation. For example, in SRAM, a key characteristic called static noise margin (SNM) can determine the voltage difference between logic 0 and logic 1 states of the bit cell, which guarantees the cell's reliable operation.
As previously covered on All About Circuits, SureCore’s SRAM technology employs a cascode precharge sense amplifier (CPSA) to control the bit-line swing and reduce the overall power consumption of the SRAM. This technology reduces the active and leakage current of the device and cuts the power demands of the SRAM.
Independent banks of one of SureCore's low-power SRAM products, EverOn. Here, one-quarter of an SRAM instance and its shared peripheral interface are active, while another quarter is asleep in a reduced leakage state. The other half is shut down, reducing even more leakage but not retaining data.
SureCore is not alone in the race to create cost-effective, low-power cryogenic memory for AI workloads. Rambus, for example, has also dedicated R&D towards cryogenic memory as part of a dedicated research program.
All images used courtesy of SureCore.
