RISC-V Summit Europe News—Processor IP, Verification Tools, and More

It’s been a big week for open-source processors as the RISC-V Summit Europe takes place in Munich. Throughout the summit, developers from various industries have been presenting their latest works to highlight the flexibility and increasing maturity of the RISC-V ISA. This article takes a closer look at three new developments, and gives readers a sense of how they could be useful to the future of the RISC-V design process.

 

Flexible RISC-V IP from SiFive

Up first, SiFive has announced the 4th generation of its SiFive Essential product family, built to provide embedded designers with improved performance. Despite the open-source nature of the RISC-V ISA, more often than not designers would choose to forego the low-level design process and instead use commercially available IP. As a result, the flexibility and performance of RISC-V IP can directly correlate to improved performance across the entire industry.

 

The SiFive Gen4 family is available in a variety of flavors, allowing designers to select the core to best meet their embedded needs. Image used courtesy of SiFive

 

The SiFive Essential Gen 4 offerings build upon previous generations of RISC-V IP available from SiFive. In terms of performance improvements, SiFive has reported that the 4th generation supports more powerful processors with better power efficiency. Though we cannot currently quantify the performance improvements, SiFive has reported a 40% runtime power reduction.

The Essential Gen 4 series provides a wide range of processors for designers to choose from, from 2 stage to 8 stage processors and 8 different embedded cores. The processors also support many software tools such as Linux, FreeRTOS, and many others. The SiFive Essential Gen4 products are available now, says the company.

 

Breker RISC-V System Verification

Next up, Breker Verification Systems has unveiled its RISC-V CoreAssurance and SoCReady SystemVIP verification suite, providing designers with new testing performance at every stage of the design process. Especially as core architectures and SoC complexity continue to increase, designers across the board can benefit from improved verification capabilities in the Breker software stack.

 

Throughout the embedded design process, verification plays a key role in ensuring that software and hardware both perform as expected. Image used courtesy of Parasoft

 

As many engineers are painfully familiar with, designing a device is not as simple as simply connecting blocks together. Comprehensive test and analysis is required before, during, and after device fabrication to make sure the device works and understand why it may not. As a result, the capabilities of the CoreAssurance and SystemVIP stacks could provide many benefits to designers.

Built into the software are tests and verification routines ranging from ISA compatibility (randomized instructions, test scenarios) to AI-enabled sequential testing and analysis to begin from a desired end state and working backwards to identify bottlenecks or performance degradation. The software can be used at any stage of the design process and is available now from Breker.

 

RISC-V AI from Semidynamics

Concluding this roundup, Semidynamics has announced the efficiency data for its RISC-V Tensor Unit, built to enhance AI performance in the RISC-V ISA. Compared to traditional computing, the data-heavy nature of AI and machine learning can quickly highlight inefficiencies at any point in the computing chain. As a result, the Semidynamics Tensor Unit could offer designers improved efficiency for AI-focused RISC-V cores.

 

Compared to traditional architectures, the Semidynamics approach removes the need for a bus, allowing for reduced data movement and improved performance. Image used courtesy of Semidynamics

 

Compared to a traditional system, the Semidynamics Tensor Unit unifies the functions performed by the CPU, NPU, and GPU into a single device, removing the need for buses that can introduce inefficiencies in advanced computing. Using the LlaMA-2 7B-parameter model, the Tensor Unit showed utilization above 80% for most data shapes. 

In addition, the Tensor Unit efficiency is evaluated for a variety of matrix sizes, with results showing good efficiency above 70% regardless of the matrix sizes. In other words, the Semidynamics Tensor Unit could offer extremely good performance for common AI operations.

 

A Bright RISC-V Future

While the developments covered here represent only a fraction of what was presented at the 2024 RISC-V Europe Summit, each of them indicate a broader trend toward increasing RISC-V utility and adoption. As more information is available, it will be exciting to see not only how the advancements shown here evolve, but how the broader RISC-V market continues to change to compete with others in the industry.

 

Featured image used courtesy of RISC-V International