RISC-V Rollouts Abound at This Week’s North America RISC-V Summit

As the RISC-V Summit 2023 comes to a close this week, many organizations have announced new innovations and initiatives in the RISC-V community to make the architecture more accessible to new designers. Compared to other instruction set architectures (ISAs), the RISC-V ISA is unique in that it is entirely open-source, allowing a wide range of organizations to use the ISA in the latest and greatest developments.

The open-source nature of the ISA makes RISC-V a constantly evolving community, with developments in software, hardware, and commercial devices being made very rapidly. This article takes a closer look at three of these recently announced developments, and gives readers a sense of the broader trends that highlight the unique features of the RISC-V ISA.

 

AI-Accelerated IP

First up, Synopsys has announced a new addition to its ARC Processor IP family, the ARC-V family, that is based on the RISC-V ISA. This new family leverages the ever-expanding RISC-V software ecosystem to provide designers with more options in hardware and software to meet their specific needs.

 

Synopsys ARC-V IP allows designers to target high-performance or low power designs with RISC-V, adding new applications to the ISA. Image used courtesy of Synopsys

 

Included in the new IP family are high-performance, mid-range, and ultra-low power options to address designer needs across a broad range of applications. The ARC-V processor family is supported both by the Synopsys MetaWare dev kit, as well as the Synopsys.ai full-stack EDA suite to provide designers a turnkey development environment to reduce time to market and improve results using the ARC-V family, all the while reducing the barrier to entry for RISC-V.

Availability of the ARC-V Processor IP family will begin in Q2 2024 with the 32-bit ARC-V RMX embedded processor, followed by the RHX and RPX real-time and host processors.

 

FPGA-Enabled Emulation

For designers looking into RISC-V software development without requiring full custom silicon, the OpenHW Group has announced the CORE-V CVA6 Platform project with the goal of bringing RISC-V emulation to more designers. Instead of requiring physical hardware or a software-based emulator, the CVA6 platform offers a one-to-one FPGA hardware mapping to ensure accuracy when moving from emulators to hardware. More information is available on the CVA6 GitHub page.

 

Using an FPGA to represent a completed RISC-V CPU allows designers to emulate real hardware in a robust environment. Image used courtesy of Aldec

 

While a hardware equivalent may seem unnecessary, an FPGA implementation allows designers to rest assured that the software being developed takes into account the finer details of the hardware involved in a RISC-V CPU. As such, software can be developed to be more robust sooner in the design process, allowing for greater innovation.

 

Data Center-Grade Performance

Rounding out the RISC-V developments, Ventana has introduced the Veyron V2, the second-generation of RISC-V data center processors. The company reports improvements with the Veyron V2 in performance and efficiency compared to the Veyron V1 released at last yea’s RISC-V Summit, and brings RISC-V to more applications that demand higher performance.

 

The Ventana Veyron V2 improves the RISC-V architecture’s performance in data-heavy applications, allowing designers to use the ISA in more environments. Image used courtesy of Ventana

 

Currently Ventana reports up to 40% performance improvements using a 3.6 GHz clock and 4 nm process technology. In addition, there is improved ecosystem support thanks to the RISE ecosystem initiative.

Furthermore, using Ventana’s Domain Specific Accelerator, designers can improve workload efficiency without constraining innovation, allowing for more developments to be made using RISC-V at all levels of computing.

At the time of this article, Ventana has not yet posted a product page for the Veyron V2. But the company held a session covering the Veyron V2 and this week’s RISC-V Summit.

 

An Extensible ISA

While it was no secret that RISC-V was already a pervasive ISA with many features to differentiate it from its competitors, the developments shown here demonstrate the level of extensibility offered by the architecture. Whether an application requires the best performance in the case of data centers, or ultra-low power for IoT sensors, RISC-V is able to provide an open-source solution.

As time goes on, it will be exciting to see how the ISA and designers evolve to provide more performance and better efficiency. Regardless, the trends toward broader adoption and more deployment of the RISC-V ISA highlight its potential to change the way computing is done.