Renesas Champions the RISC-V Cause With Its Own 32-bit RISC-V CPU

Renesas, long a major player in the industrial MCU and CPU universe, has announced the release of a new CPU family with a RISC-V core of its own design. The design joins Renesas’ 32-bit arsenal, which includes Arm Cortex-M-based CPUs and the proprietary RX family. The devices are targeted at the general-purpose RISC-V market for consumer, industrial, healthcare, and IoT applications.

 

Renesas ships millions of parts into the automotive industry. Image used courtesy of Renesas

 

This is not the first RISC-V-based product from Renesas, but its prior offerings used designs by third-party IP providers, such as Andes Technology. With this new offering, Renesas designed and built its own from the open-source specifications. Having its own design RISC-V instruction set architecture (ISA) will enable greater customization for products in its core markets and allow Renesas to have control over product release timelines. Ultimately, RISC-V was created to give companies this type of flexibility without the extra work and limitations that come with a fully proprietary ISA.

 

A Win-Win for Renesas and RISC-V

RISC-V (pronounced “risk five”) is an open-source instruction set architecture, originally designed as part of a 2010 research project out of the Parallel Computing Laboratory at the University of California, Berkeley. In recent years, RISC-V has gained broad acceptance and is now available as an IP package from multiple IP vendors and as hard and soft processor cores in FPGAs. 

RISC-V has been gaining wider acceptance, and a full portfolio of offerings from Renesas is a significant win for the architecture. Renesas has a large footprint in automotive, industrial, and IoT solutions. Its processor portfolio contains custom architectures, Arm-based products, and now, RISC-V CPUs. Renesas may not be the most well-known microcontroller brand, but it is one of the most widely used due to its extensive automotive and industrial control products. A general-purpose RISC-V core from Renesas may help the company grow into more diverse markets by producing a powerful component based on the up-and-coming architecture. 

 

Leveraging RISC-V Flexibility 

RISC-V allows designers to choose tradeoffs between power draw, computing power, and silicon area. A compliant system can be implemented as a simple single-core microcontroller up to a multi-thousand-node cluster of a complex shared-memory server node. The specification provides such flexibility and design economy by starting with a base integer ISA that is common to all implementations, with optional ISA specifications for more complex applications.

 

Renesas RISC-V block diagram. Image used courtesy of Renesas

 

The new Renesas processor family is a 32-bit processor, so it doesn’t need to contain support for a 64-bit RISC-V or future 128-bit RISC-V. Renesas has not yet published detailed product specifications, but it did disclose a 3.27 CoreMark/MHz performance benchmark. Renesas states that it has chosen an implementation that is efficient in the required silicon area, which will lead to lower power consumption while providing high computational throughput.

 

Renesas Cherry Picks RISC-V Extensions

Renesas chose a number of RISC-V optional extensions (M, A, C, and B) for the first processor while leaving out many other extensions that would take up silicon real estate without adding value for their intended target applications. 

“M” adds a hardware multiplier and divider unit to improve math operations based on multiplication and division. “A” brings in atomic access (uninterruptible read-modify-write access to prevent concurrency-caused errors) and important capability for RTOS operating systems. “C” adds in short 16-bit instruction encoding for common operations. This reduces program code space on the order of 25%–30%. “B” has bit manipulation instructions to speed operations with peripheral registers—a common need with microcontrollers.

Many designers use Renesas chips in real-time critical applications. Renesas optimized this RISC-V design for real-time response with an added register bank-save function in the hardware. This function will speed up the process of backing up and restoring CPU working registers during interrupt services and other context-switching events.

 

The First of Many Offerings

Renesas specializes in the automotive market, with 50% of its 3.5 billion units per year going into motor vehicle applications. This Renesas design will go into many product offerings, from applications processors to system-on-chip (SoC) processors and embedded application-specific standard parts (ASSPs). The first processor will target multi-use applications. Future uses will complement its line of third-party RISC-V motor control and voice control chips. The first product in this family will be released to market in Q1 2024.