EDA Companies Unite With Samsung for AI and 3D IC Technology

It was a busy week for Samsung at the Design Automation Conference (DAC) 2024, where the manufacturer garnered support from leading EDA providers for its two SF2Z and SF4U process nodes. This news follows the same EDA companies, Cadence, Siemens, and Synopsys, announcing support for Intel's Foundry's new process technology, including the Intel 18A node.  

 

Samsung employs a gate-all-around structure for its transistors, in which a gate surrounds all four faces of the channel where electric current flows. Image used courtesy of Samsung

 

Samsung says its new process technology, combined with its newly forged partnerships with Cadence, Siemens, and Synopsys, will enable it and foundry customers to create low-power, high-performance chips for AI workloads.

 

Samsung's New GAA SF2 and SF4 Nodes

The top EDA companies have optimized their tools for Samsung’s gate-all-around (GAA) SF2 and SF4 node technology. GAA is Samsung’s most advanced node technology, allowing node sizes as minuscule as 2 nm with up to 45% power efficiency improvement and significant gains in performance and surface area. In advanced semiconductor manufacturing, an ongoing challenge has been reducing gate length while retaining efficiency. To address this, Samsung developed the third-generation GAA structure.

 

Comparison between different FET architectures. Image used courtesy of Samsung

 

In a transistor with a traditional planar structure, significant current leakage, known as a short channel, occurs between the source and drain. In GAA transistors, the gate surrounds all four sides of the channel where electric current flows. This enables better control of current flow and enhances channel operation, resulting in higher energy efficiency.

 

Cadence Bolsters 3D IC and AI Simulation

Cadence recently announced a broad collaboration with Samsung aimed at accelerating 3D IC and AI semiconductor development. The company says it has optimized its EDA tools for analog and digital advanced node AI designs, particularly Samsung’s GAA SF2 and SF4 node technology.

Cadence says its vast Cadence.AI verification and IP suite accelerate time to market and maximize PPA for advanced process nodes. It also reportedly reduces leakage current by an average of 10%.

 

Cadence's integrated 3D IC platform. Image used courtesy of Cadence

 

Cadence.AI encompasses several different EDA tools: Cadence Cerebrus, Virtuoso Studio, Verisium, Allegro x AI, and Optimality. Cerebrus is an AI-driven digital design tool that automatically optimizes the design for maximized PPA based on desired constraints the designer inputs. Other tools in the Cadence.AI suite, such as Allegro x AI, use generative AI to reduce placement and routing (P&R) time from days to minutes. Additional features of Allegro x AI include auto-synthesis of power and ground planes and critical net auto-routing.

In addition to Cadence.AI, Cadence also has a full backside implementation certified for SF2 and the Cadence Integrity 3D-IC Platform for multi-die integration.

 

Synopsys Provides AI EDA Suite for SF2

Cadence is not the only EDA player with a suite of diverse tools for AI chip design. Similar to Cadence, Synopsys also provides a full-stack EDA for AI called Synposys.AI in collaboration with Samsung for SF2 GAA. Synopsys says its SF2 IP is “silicon proven” with multiple tapeouts. One differentiator that sets Synopsys.AI apart from Cadence.AI is its production data analytics tool, Silicon.da.

 

Silicon.da provides post-silicon insights for design improvement. Image used courtesy of Synopsys

 

Silicon.da has a wide array of functionality but stands out because it can be used in a production test feedback loop. By taking real-time data inputs, it can give control instructions to the production test facility to maximize cost savings and quality through fine-grained binning based on leakage and performance measurements. 

 

Siemens Offers Digital Twins for Multi-Die Chips

Siemens is also collaborating with Samsung to support the GAA SF2 technology. Multi-die chips are becoming increasingly common in AI-chip architectures. Siemens offers a platform that creates a “digital twin” model of a multi-die chip for easier die integration in complex designs.

Digital twins eliminate the need for prototypes through advanced simulation technology. Siemens' XPedition Substrate Integrator (XSI) technology can create digital twins for 2.5D/3D chips with different packages, PCBs, and interposers, with no need for physical prototypes.

 

Siemens' Xpedition Substrate Integrator can integrate die, chiplets, and interposers from different process nodes and suppliers. Image used courtesy of Siemens

 

Siemens has also certified multiple flows for SF2. For example, Samsung has certified several Siemens products like Calibre xACT 3D and Analog FastSPICE (AFS) across various process nodes, ensuring accurate design verification and robust performance for applications in 5G, automotive, and AI industries. Siemens aims to increase customer confidence in designing for GAA SF2 through these certifications and EDA tools.