Codasip Claims ‘Best-in-Class’ RISC-V Core for Power-Conscious Designs
The L110 embedded RISC-V processor core is highly configurable using the new Codasip Studio Fusion design automation toolset.
Munich-based Codasip, a leading vendor of RISC-V processor solutions, has released the Codasip L110, a highly configurable embedded processor core designed for the most power-sensitive processing applications.
The Codasip L110.
The L110 architecture is highly configurable via the Codasip Studio Fusion processor design automation toolset, allowing customers to optimize their processor designs for power, performance, and area (PPA) as required by the end application. According to Codasip, the new L110 core delivers up to 50% more performance per watt with 20% less code size and is a useful processing solution for space-constrained, low-power applications like sensor controllers and IoT edge devices.
Codasip L110 Core
The Codasip L110 is a 32-bit RISC-V embedded processor architecture designed for compact and low-power applications like edge sensors. The base core (in-order, three-stage, single-issue pipeline) is highly configurable with several standard options to select from: RV32I/RV32E, multiplier (sequential and parallel), or B, C, or Z extensions.
The architecture also includes physical memory attributes (PMA) with 16 regions, a configurable interrupt controller (CLIC), and individual data and instruction AHB-Lite bus protocol interfaces for communication to and from peripheral devices.
Codasip L110 embedded RISC-V processor.
According to Codasip's chief commercial officer Brett Cline, the configurability of the L110 allows designers to quickly include new instructions for their embedded software to optimize for PPA with no risk to the core functionality.
Codasip Studio Fusion
Codasip Studio Fusion is the latest version of the Codasip toolset, which generates the register transfer level (RTL) and software development toolkit. A user-friendly graphical interface allows designers to explore the range of configuration options for the processor easily without processor design experience.
Codasip Studio Fusion graphical user interface (GUI).
Using the development software, custom instructions can be added to the L110 without risk to the baseline core's functionality.
The Merits of RISC-V for Licensing Models
RISC-V is an open-specified Instruction Set Architecture (ISA) maintained by RISC-V International, of which Codasip is a member. Its purpose is to offer designers an open-source alternative to proprietary and closed-sourced ISAs like x86 and Arm. While RISC-V is not a processor design itself, cores designed using the RISC-V ISA can be either open-sourced or commercially licensed.
Codasip makes the L110 core IP accessible through two licensing models. The Codasip standard license includes the standard core IP delivered in RTL for direct use in the end application. An enhanced architecture license adds the full CodAL high-level description language, allowing for full customization of the base core.
Growing Demand for Low-Power Processors
As system designers seek to increase access to new data streams, the demand for remote sensors will continue to grow. Codasip designed the L110 as an affordable solution for the next generation of IoT edge sensors and similar low-power devices that need high-performance embedded processing with as little power consumption as possible.
All images used courtesy of Codasip.
