Verifying the True Jitter Performance of Clocks in High-Speed Digital Designs

Application Note Overview 

Measuring jitter for clocks in high-speed digital designs has become increasingly challenging. PCIe 5.0, for example, uses data rates of up to 32 gigatransfers per second (GT/s) with a corresponding jitter limit of 150 fs (RMS) for the reference clock. Data rates of 64 GT/s are introduced with a 100 fs jitter limit for the reference clock in the latest PCIe 6.0 specification. As the data rates in high-speed digital designs increase, the limits for overall system jitter become tighter. Due to their high phase noise sensitivity, phase noise analyzers are the instruments of choice for these tests.