PAM4 Gigabit Ethernet Electrical SERDES Analysis, Debug, and Compliance Testing

White Paper Overview

To address the 30+ dB loss experienced by 25+ Gb/s electrical signals on PCB (printed circuit board), the 50/100/200/400 Gigabit Ethernet standards are replacing the NRZ (non-return to zero) modulation scheme with PAM4 (4-level pulse amplitude modulation). 

PAM4 brings a host of complications: gray coding, interleaving, FEC (forward error correction), three eye diagrams per UI, a 9.5+ drop in SNR, shift from jitter-limited to noise-limited analysis, and signal nonlinearities such as eye compression.

Demonstrated in this Anritsu white paper is how the introduction of complicated figures of merit such as SNDR, COM, and ERL, in addition to FEC, changes how we think about SERDES performance. SERDES tests require more than pristine signal generation and error counting. Presented are key SERDES tests, the need for FEC test patterns and the ability to insert errors that can probe Reed-Solomon FEC, and techniques for calibrating interference and jitter tolerance tests.

This white paper works through PAM4 error analysis — both BER and SER (bit and symbol error rate). Topics discussed include the need to analyze each of the 12 symbol transitions, read a SERDES's FEC counter, and error triggering so that error distributions can be analyzed and the raw BER can be reconciled with the FEC BER.